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33 from Perseus Tools and Information

1. Cove on Mount Olympus Place: Utah, United States [Atlas site] (17.36)

2. Olympos [Atlas site] (11.70)

3. Lympus, Olympus: Vermont, United States [Atlas site] (10.80)

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82 from Greek and Roman Materials

1. LYCAEUS [Reference article in Dictionary of Greek and Roman Geography (1854) (ed. William Smith, LLD)] (13.70)

2. Lycaeus [Reference article in Perseus Encyclopedia] (13.02)

3. Lycaeus [Reference article in Harry Thurston Peck, Harpers Dictionary of Classical Antiquities (1898)] (11.97)

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51 from Beazley Archive

1. New York (NY), Market, Emmerich: LEKYTHOS; EDINBURGH PAINTER; INTRODUCTION OF HERAKLES ON OLYMPOS (HERMES, ATHENA, HERAKLES, IOLAOS ?), COLUMN [Beazley Archive Vase] (11.06)

2. Naples, Museo Archeologico Nazionale, H3235: PANATHENAIC AMPHORA; NAPLES 3235, GROUP OF; OLYMPOS WITH LYRE AND MARSYAS WITH PIPES, BOTH NAMED AND SEATED, WOMEN, ONE NAMED (THALEA), YOUTH SEATED, SATYR AND MAENAD WITH THYRSOS (NAMED; THYRBA, ORAGIES, THEFT OF THE PALLADION, DIOMEDES WITH SWORD, HELENA, ODYSSEUS IN PILOS AND CHLAMYS WITH SPEARS AND SWORD, ALL NAMED, POST [Beazley Archive Vase] (11.06)

3. St. Petersburg, State Hermitage Museum: BELL-KRATER FRAGMENTS; DIONYSOS AND ARIADNE, WITH SATYRS AND MAENADS, INTRODUCTION OF HERAKLES TO OLYMPOS; ABOVE: ZEUS, HERA, ATHENA AT CENTRE, BELOW: DIOSKOUROI, ATHENA, HERAKLES [Beazley Archive Vase] (8.37)

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7 from CIMI Metadata Harvesting Working Group Demonstration Repository

1. (in English) 26 AND 1/2 X 39 INCHES MT OLYMPUS LAKE ST CLAIRE BY W C PIQUENIT [Text] (7.71)

2. (in English) 215 x 470 x 475 mm. T-shaped stand with light fitting (x-ray ?0, quadrant shaped stem, adjustable stage, substage condenser, 4 space for objectives in rotatable mounting, binocular body (one eyepiece adjustable), camera fitting at top of the body, body tube fixed, stage height adjustable. Inscribed : ,E LEITZ / WETZLER / GERMANY/ Nr 516100, On base ; ditto without number on clip guide rail ; ,ERNST LEITZ/ GmbH/ WETZLER/ GERMANY/ 1.25,, On body tube ; ,C 1.25X,, On binocular body. ; ,ERNST LEITZ/ GmbH/ WETZLER/ 8x B PERIPLAN, On both binocular eyepieces ; ,OLYMPUS/ TOKYO 125 FK2.5X, Japan on monocular eyepiece ; ,STANFORD/ X-RAY CO PTY LTD/ B.M.A. House/ 135 MAQUARIE ST/ SYDNEY, N.S.W.,, On metal plate. Good. [Text] (2.75)

3. (in English) OLYMPUS GASTRO CAMERA / GASTROSCOPE SET ?1960 IN WOODEN CASE - 530x420x100mm [Text] (1.97)

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1 from NCSTRL Historical Collection

1. Gupta, Rajesh Kumar; Co-Synthesis of Hardware and Software for Digital Embedded Systems: As the complexity of systems being subject to computer-aided synthesis and optimization techniques increases, so does the need to find ways to incorporate predesigned components into the final system implementation. In this context, a general-purpose microprocessor provides a sophisticated low-cost component that can be tailored to realize most system functions through appropriate software. This approach is particularly useful in the design of embedded systems that have a relatively simple target architecture, when compared to general-purpose computing systems such as workstations. In embedded systems the processor is used as a resource dedicated to implement specific functions. However, the design issues in embedded systems are complicated since most of these systems operate in a time-constrained environment. Recent advances in chip-level synthesis have made it possible to synthesize application-specific circuits under strict timing constraints. This dissertation formulates the problem of computer-aided design of embedded systems using both application-specific as well as general-purpose reprogrammable components under timing constraints. Given a specification of system functionality and constraints in a hardware description language, we model the system as a set of bilogic flow graphs, and formulate the co-synthesis problem as a partitioning problem under constraints. Timing constraints are used to determine the parts of the system functionality that are delegated to application-specific hardware and the software that runs on the processor. The software component of such a 'mixed' system poses an interesting problem due to its interaction with concurrently operating hardware. We address this problem by generating software as a set of concurrent fixed-latency serialized operations called threads. The satisfaction of the imposed performance constraints is then ensured by exploiting concurrency between program threads, achieved by an inter-leaved execution on a single processor system. This co-synthesis of hardware and software from behavioral specifications makes it possible to build time-constrained embedded systems by using off-the-shelf parts and application-specific circuitry. Due to the reduction in size of application-specific hardware needed compared to an all-hardware solution, the needed hardware component can be easily mapped to semicustom VLSI such as gate arrays, thus shortening the design time. In addition, the ability to perform a detailed analysis of timing performance provides an opportunity to improve the system definition by creating better prototypes. The algorithms and techniques described have been implemented in a framework called Vulcan, which is integrated with the Stanford Olympus Synthesis System and provides a path from chip-level synthesis to system-level synthesis. [Text] (0.98)

2 from The University of Michigan. University Library. Digital Library Production Service.

1. Wheeler, Professor D. H.; Shakespeare's Olympus, The Ladies' repository: a monthly periodical, devoted to literature, arts, and religion. [Text] [View with Perseus links] (4.54)

2. Wheeler, Prof. D. H.; Shakespeare's Olympus, The Ladies' repository: a monthly periodical, devoted to literature, arts, and religion. [Text] [View with Perseus links] (4.42)